HBM offset iTHOP alignment issue

 The offset between HBM and iTHOP is causing the alignment challenges.

Given the differences in expansion between silicon chip and organic interposer substrate, there is potential for cracks or delamination by the high stress generated by the newly formed interconnections. The solder integrity was verified with X-ray and peeling test. The optical observation of the samples after chip pulls on the iTHOP showed that flip chip pad were pulled out with the chip, implying the good adhesion, and hence good joints. Samples were then subjected to reliability stressing to downselect the optimal process for subsequent study.

In the case of TCB process, the substrate is heated and chip joint while it is held to the stage by vacuum.

The large chip size maybe arranged assemmetrically with respect to the center of the substrate. Pads on an organic substrate fluctuate in planar position due to the expansion and contraction of the substrate material as the substrate is heated and cooled. The amount of pad fluctuations varies greatly from place to place.

By applying appropriate compensation in the circuity design of the organic substrate, the micro bumps and pads are designed to align at the temperature at which the solder melts during chip bonding .If the compensation value is not set correctly, it is difficult to ensure good bonding. Even if the center of the chip is perfectly aligned, the further away from the center of the chip, the more serous alignment becomes. If the chip size is small, the degree of misalignment at the edge of the chip will be relatively small. 

The direction of distortion depended on the position of pads.

HBM introduction

The special memory which powering deep learning revolution & AI

MI300: AI acceralator which use HBM

HBM does not refer to a special type of dynamic RAM memory cell or special chip.Rather it is a standard administered by the Joint Electron Device Engineering Council or JEDEC - for interfacing the DRAM and the compute. HBM introduces the concept of stacking the DRAM dies and running many independent memory channels through the stack. The goal is to provide very high data rate transfers for more advanced computing applications like those for AI which are more amenable to parallelism. The vendor can also choose to add a logic base die - as is  shown in the JEDEC spec diagram. This additional logic is for redistributing signals, test logic, and other external commnuncations. JEDEC's standard defines for the manufacturer how the HBM system has to work and what features they need to support. It helps with the commands and signals sent through the memory channel in the DRAM stack, for instance. But it does not specify how the vendor might structure the stack nor does it specify things outside the stack. This allows various HBM vendors in the memory industry to offer a differentiated products. HBM buyers can put your HBM stack right on the top of your CPU or GPU die. Or do what AMD/NVDIA which is to add a silicon interposer to connect multiple HBM die stacks to your GPU-like a PCB. JEDEC also administers other standards like DDR, LPDDR. 

    DDR is the standard you might be most familiar with- used for general purpose memory modules like those you put into your PC. The traditional memory interface standard for graphics cards is GDDR or Graphics Double Data Rate. Right now they are on their sixth generation-GDDR6. There are few gaming cards using it. Why do we need another standard? There are a few things that make it less suitable for heavy AI processing. First, while each new GDDR standard does feature higher data rates, they also employ a point-to-point connection. This means that each memory channel connects to just one module of memory. This is in contrast to HBM, where channels run through all the modules in the stack. GDDR's single channel makes it harder to scale the system's total memory capacity because it means we have to scale that single module's memory capacity which essentially requires us to shrink down DRAM cells even more which is hard, I did a whole video about this while ago discussing the 3D DRAM cell. 

    Future shrinks seem to require new capacitor structures like the pillar which may or may not be actually manufacturable. By vertically stacking the modules, HBM makes it conceptually easy to raise the memory capacity. There are also some physical size gains as well when it 

Reply the concerning about the failure analysis method

    As we know that the samples from substrate side has been grounded down to be thinner, it has resulted in an uneven surface. Due to this uneveneess, when you removed the chip from the top side, the microbump pad may not all to be exposed at the same surface level. This non-uniformity could potentially affect the open short test results as they probably not to make the consistent contact with their corresponding counterparts.

    The thickness of the samples after removing chip also is very concerning. Cold mounting may not be suitable for extremely thin samples. This method cannot precisely targeted to the desired positions or it does not compromise the sample's structural integrital. The air bubbles or voids may form during embedding process, affecting subsequent analysis. It should be more risky than previous PFA proposed by PTI.

    I confirmed with PTI related person, PTI did not have available test kits with fine probe. Anyway,  I still asked these questions to Shinko Japan, we are still waiting their answers. I can predict the answer is not promising.

How to reply customer about the failure analysis time

     At this stage, we are awaiting for internal approvals, which may take some time.

    Once approved are secured, we will expedite the failure analysis procedure and provide you with an estimated completion time for the failure analysis.

UMI HBM P1 PJ preliminary design review

    Today I would like to present a preliminary design phase of the UMI P0 project. The body of the HBM package measures 65x55x4.5mm, the package type is HSFCBGA, it contains 1930 balls. The HBM cube is made of PTI P8 site and the flip chip assembly site is in P11B site. Here is the list of roles related to this project, product engineer is Chris and Sales is Ted.

The purpose of design review is to provide sufficient information, evaluate progress, technical adequacy, and risk resolution of the selected design approach, to determine the each design's compatibility with the requirements for the configuration items, to access the technical risk associated with the selected manufacturing methods and processes, to establish the existence and compatibility of the physical and functional interfaces among the configuration items and other items of equipments, facilities, software, and personnel.

    This is the milestone of UMI P1 project was kicked of by Nov of last year. All drawings have been approved by next month December, and the preliminary design review has been finished on January of this year. We estimate will start the setup & ES from end of May. The HBM cube is made of PTI P8 site and sent to customer for finat testing and return the know good dies to PTI for proceeding the corresponding flow. The cube is diced and secured in metal ring frames, and then transport to another site. And now all the related tooling kits has been arrived at PTI and ready for setup.

    This page demonstrates that the overall P0,P1,P2 project structure, application and status. All of them will be applied for AI or High performance computer. This three project has no big differences but only package size and different wafer node. PTI will start to build HBM cube since from P1 project. UMI managed all the consigned direct material in assembly for the P0 project and has shipped out the package to UMI by end of last year. Estimate to build QT samples from this end of year and HVM will be next year. UMI & PTI are cooperating design drawings rcently.

    The overall project information was published by UMI, which included the HBM, SOC, organic interposer and package substrate. HBM cube of P0 was provided by UMI but customized by UMI in P1 &P2 . All these projects shared the same TSMC SOC wafer with 1pcs wafer. They also shared the same organic interposer with the same 2um/2um line space, 6L and 40/40um line space with 10 layers build up substrate.

    The ES samples of P0 project has been shipped out to UMI before the end of last year. Here is the overall related flow, direct, indirect material & Tooling kits preparation schedule for your reference.

    As we knew that all the material consigned by customer for P0 project, when PTI received the HBM/SOC/ iTHOP, PTI utilized thermocompression bond on iTHOP, and filled the gap between chip and substrate with capillary underfill. The stiffiner ring are bonded on the substrate, and then flipped the package for SMT & ball mounting.

To stack and connect bumped dies in package, PTI uses thermal compression bonding. After peeling the HBM/SOC chip side & iTHOP side, the remained solder amount appeared that the solder joint strength is robust enough. The samples has been executed the cross sectional examination with SEM, the bump gap between chip & iTHOP is close to the design value. The X-ray test results analyzed the placement accuracy of TCB meet the specifications.

     The top director has announced that the 1st HBM cube could be finished by the end of May, the flip chip AP must be ready for setup & ES to meet the development schedule. The lower diagram showed that the basic flow of P1 project, the incoming wafer B will do the microbumps , Backside grinding, wafer mount and dicing, for the incoming A will the PI firstly and then do the microbumps and copper pillar bumps correspondingly. At the BEOL site, PTI mount the die B on the die A with CoW process, and then molding. For the mold grinding, the rough grinding Z1 will be processed in P8 but the fine grinding processed in P11. After grinding, copper pillar bump will be done on the Cu post.

To make a copper bumps, a surface is depostied with an under-bump-metallurgy, then, a photoresist is applied on the UBM, the desired bump size is patterned and etched, forming a small gap in the resist. A copper layer is plated on a surface, forming a pillar in the gap. The material is reflowed or heated, froming the bump.

Introduce myself as a new collaegue

Hope you are doing well! 

I hope this message finds you well.

My name is Christine, and I am excited to introduce myself as a new team member and will be collaborating with you on this project.

I am eager to contribute to our collective goals and learn from each of you.

and I am reaching out to you as the new colleague who will be taking over this project.

I understand that transitions like these can sometimes be challenging, but please know that my primary goal is to ensure a smooth handover process and to maintain the momentum of the project. I am committed to upholding the standards of excellence set by Kevin Wang and to continue building on the progress made so far.

To give you a bit of background about myself, I have relevant package design experience in PTI over 12 years, especially in relation to the Intel project. I am excited about the opportunity to collaborate with you and the rest of the team to drive this project forward successfully.

I would greatly appreciate the opportunity to connect with you at your earliest convenience to discuss any ongoing tasks, objectives, or concerns you may have regarding the project. Please let me know a time that works best for you, and I will make myself available.

Thank you for your cooperation and support during this transition period. I look forward to working closely with you and the team to achieve our shared goals.

------------------------------------------------------------------------------------------

I hope this email finds you well. My name is [Your Name], and I'm excited to introduce myself as your new colleague who will be collaborating with you on the [Project Name] project.

I understand the importance of effective teamwork in achieving project success, and I am eager to bring my skills and expertise to the table to contribute to our collective efforts.

In my previous role at [Previous Company/Project], I [briefly mention relevant experience or skills]. I believe that my background in [mention relevant skills or expertise] aligns well with the objectives of the [Project Name] project, and I am committed to working collaboratively with you to achieve our goals.

I am looking forward to learning from your insights and expertise and to leveraging our combined strengths to drive the project forward. I believe that open communication and a spirit of collaboration are key to our success, and I am committed to fostering a positive and productive working relationship with you.

Please feel free to reach out to me at any time to discuss the project further or to share any thoughts or ideas you may have. I am here to support you in any way I can and am eager to get started on our collaboration.

Thank you for welcoming me to the team, and I am excited about the opportunity to work together on the [Project Name] project.

Request for P0 Samples Build Plan and Consigned Material Arrival Estimate

 Dear Okutso San

I hope this message finds you well.

As we proceed with the samples build for P0 project, we want to ensure a smooth and efficient process.

To facilitate this, we kindly request with your assistance with the following:

1. Samples Build Plan

We understand your request for 5 pcs of the sample. To streamline the setup process effectively, it would greatly benefit us to prepare at least 30pcs for the program re-setup in advance. This will enable us to optimize our procedures and ensure the quality of the samples meet your expectations. Could you please confirm if this arrangements aligns with your requirements?

2. Estimated Arrival of Consigned material- iTHOP SBT & Stiffner

Additionally, to sychronize our production schedule and accomodate any necessary preparations,  we would appreciate an estimate of when the consigned material is expected to arrive at our facility. This information will enable us to plan our resources accordingly and ensure a timely commencement of the sample build process.

Your cooperation in providing these details will greatly assist us in delivering the best possible outcome for this project. Should you have any questions or require further clarification, please don't hesitate to reach out to us.

Thank you for your attention to these matters. We look forward to your prompt response.

Improper packing method from vendors

 Dear Shinko pals,

Regarding to the recent shipment we received from your company, I regret to inform you that the package arrived in a less-than-satisfactory condition due to the improper packing methods. Upon receiving the package, it was evident that insufficient care had been taken to secure the contents adequately. (Describe the specific issue, such as inadequate cushioniong, loose items, )

As a valued vendor, we trust in he quality of your products and services. However, it is crucial for us to receive shipments in a condition that reflects the standards that we have come to expect from your company. Inadequate packing not only jeopardizes the integrity of the goods but also poses risk during transit.

To prevent similar incidents in the future, we kindly request that you review your packing procedures and ensure that all shipments are securely packaged to withstand the rigors of transportations. Proper packing not only protects the items being shipped but also upholds your reputation as a reliable supplier.

We would appreciate your immediate attention to this matter and any steps you can take to rectify the situation. Additionally, please advise us on how you plan to improve your packing procedures to prevent such occurence in the future.

Thank you for your prompt attention to this matter. We value our partnertship and look forward to your shift resolution of this issue.

Proposal for physical failure analysis services

Hi Okutso San

I hope this message finds you well. I am collaegue of Kevin Wang and I am taking over this P0 PJ pFA case. Upon receiving this delicate samples which has smaller bump with finer pitch, there is a concern that they may deform too easily after removing substrate with an inherent risks that can lead to failure. We would recommend to outsource to 3rd party with experienced knowledge and advanced technology.

after removing the BU substrate.We would recommend to cold mounting resin to preserve its mircostructure. And then precisely grinding to the desired thickness.

Given their delicate nature, there is a concern that they may deform too easily after removing the build up substrate. We understand the importance of obtaining the accurate and reliable results, and this case, we would recommend to cold mounting of the samples before removing the build up substrates.

The FIB analysis on an hourly basis, and the charges are calculated accordingly.The complexity and duration of the cross sectional examination process can vary depending on several factors, including the desired depth of analysis, the nature of the samples.

We've committed to assisting  you in any way we can to achieve your research objectives, so please feel free to reach out to discuss potential solutions or further clarification on this matter.

Thank you for your understanding and cooperation.

Best regards.

Objective:

To identify the root cause of the failure, validating the process thermal compression bonding condition

Scope of work:

1. Sample preparation

• Cold mounting of the samples to preserve its mirostructure
• Precision grinding to achieve the desired thickness, ensuring minimal damage to the sample

2. Cross-sectional study

• Conducting a cross-sectional examination to analyze its internal structure
• Utilizing microscope technology SEM to observe any defects, or anomalies

3. Analysis and Reporting

• Interpreting the findings from the cross-sectional study
• Providing a detail report with comprehensive analysis

Timeline:

Provide an estimated timeline for completing each phase of the project, from samples preparation to final report delivery. Ensure that the timeline is realistic and accounts for potential challenges or delays.

Cost:

Present a break down of the costs associated with the physical analysis services, including labor, materials, and equipment usages. Be transparent about any additional fees or expenses that may arise during the project.

UMI P1 Flip Chip process flow

Milestone

Drawing已經確認完成並且在1/9進行pre-DR meeting, tooling kits基本上都已經到廠內了HBM cube的部分是在P8做,預計會在5月底前會使用ES3 recovery wafer到P11作flip chip封裝

UMI Overall Project Status(標準customer information)

P0從去年12月就有封一些樣品給客戶做測試, FT test pass.不過這只是HBM model
那真正量產的Device會是從P1開始, design 部分是在去年完成的
P2目前還在設計階段

Overall PKG information 的文件資料 其實跟先前是一樣的
P0是之前都是客戶的consign 材料 我們只做一些封裝
P1之後開始都是由P8開始做HBM cube 再送到P11作封裝
SOC部分是客戶提供一片 共用在P0/P1/P2 project上面

這是P0去年12月中做的封裝/樣品數量/封裝和測試的主要流程

收到來料Shinko含interposer的iTHOP SBT裡面的L/S 是2/2線路的 SOC 的bump pitch是45um & HBM2的Bump pitch是55um, 用TCB bonder COS方式bond 這三顆晶片 在用underfill在interposer上面做gap filling 在上stiffner ring在翻轉過來做電容SMT 然後在做ball mount P0 大致上就是這五大流程 主要是在P0的時候主要的關鍵站在HBM &SOC & interposer之間殘留錫部分有沒有joint 用SEM確認成形後bump gap確認是否有在我們的預測範圍內 die gap看起來差不多38um 都很接近設計值 有確認到TCB bump joint 用X-ray確認到chip to interposer bump to pad 的之間 確認是否有偏移的狀況 目前看起來都很正常 沒有問題 能力檢查部分都沒問題

P1 客戶提供兩種Wafer die   & die B 細部流程會在後面詳述
 Die B會在P8先做Backside grinding /wafer mount/ dicing 只做front side mirco bump
而Die A部分一樣在P8的back end 的CoW 當站用TCB mount die B 上去die A 然後在做wafer form molding 然後再進行mold grinding MDG有分Z1 (粗磨)& Z2+Z3(細磨) 由於P8就只有粗磨 所以Z2 & Z3會在P11B作業 做完mold grinding 之後又回到P8做最後一道copper pillar bump 然後在P8做wafer mount & dicing  然後再到P11解ＵＶ後做TCB　在做ＨＢＭ封裝

Die B主要是在front side長bump 然後wafer thinning & wafer dicing 以切完單 M-ring tape方式 一起進backend 的COW

Die A 的話在front side先做RDL 然後在coating PI 然後再長micro bump & copper post 主要是這四大流程  然後會以wafer form 方式shipping 

接下來講封裝部分 會以die A為基底  用TCB bond Die A 到Die B上面 做完chip on wafer 之後 molding 在做mold grinding  然後在做最後一道copper pillar bump 最後HBM cube dicing以tape & reel方式shipping 到P11B 大體上後面封裝跟P0是一樣的

Shinko會把organic interposer mount 在10L ABF SBT 上面 主要是以NCF方式bonding 
line/space:2/2 pad pitch :40um thickness:100um
Process flow 主要是以supporting carrier 去做rigid layer formation 主要是以壓合方式去做rigid layer做carrier 在做chemical /mechanical polishing  在做thin film的formation 在做4層的RDL  coat曝光顯影 4+1 去掉support carrier之後做solder printing 這是錫鉍SnBi 在貼NCF在dicing 當下面的10L ABF 做完  經過封裝流程 bond interposer 在10L ABF SBT 

POD& 卡通圖的對應 用1~6 的示意圖來表示

從P8哪裡得來料使用D185 已經切單好,只要解UV(大概200mJ)就可以在P11pick up die ,一開始先SBT prebake, SBT來料是以unit type 放在tray 盤上面, SBT prebake之後就要轉移到boat 盤進行TCB bond,從flux clean 到tray 之間的作業需要用到standard 的boat 來進行作業, 所以需要有這個流程, 轉換standard boat之後就可以做flux clean, 再prebake, 再上underfill前做plasma 清洗,點完膠之後再做curing 然後AOI,之後在上stiffiner再烤乾,就可以反面做電容SMT, 看完SMT AOI之後就可以做ball mount, 這時候就可以轉到tray盤, PD會提供tray 盤, 再做OS跟AOI

目前只有try to boat & boat to tray 的站點 沒有boat to standard boat的站點
SAP+ES+MES串好   797/798 tray to TCB boat & boat to standard boat 命名站別
需要拉開來 避免混淆 EE&ME確認是否可以新增設備名稱(公安需要審核) 再綁新的站別
5月中三合一的站別需要變更
斗哥&Derek串好 先暫用標準流程先跑 未來會變更

GX料號是客戶consign 料號, ring 先用客戶

電容5S & 5B都會用到
三家tray 都已經到PTI了 到時候會先看看作業性&外觀就會提供給相關人員

How to write meeting minutes

 1. Preparing

-->write the agenda

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2.Writing

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-->Facts or things happened write down and share them to participants

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3. Re-writing

-->spelling errors, maybe  big differences , in order to let anybody understand them

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5.