Arco 2P T62M 32D (14 x 15 x 1.915 mm) Package
Technical Risk Assessment (TRA) Summary
Package Information
| Item | Specification |
|---|---|
| Package Size | 14 x 15 x 1.915 mm |
| Controller Die | 3.4 x 4.3 x 0.10 mm |
| DRAM Die | 6.8 x 10.9 x 0.045 mm |
| Die Attach Film | 20 μm (Bottom 4 dies), 10 μm (Upper 28 dies) |
| Substrate Thickness | 370 μm (100 μm Core + 20 μm Prepreg) |
| Mold Body Thickness | 1151 μm |
| Chip-to-Mold Clearance | 101 μm |
Key Technical Risks
1. Die Mark Exposure Risk
Risk Description
- Due to the relatively thick die stack and limited mold cap thickness, the top die surface may become exposed after molding.
- DRAM thickness variation may further reduce mold coverage margin.
Potential Impact
- Die mark exposure.
- Cosmetic defect and reliability concern.
Recommended Action
- Tighten incoming DRAM thickness tolerance control.
- Verify mold cap coverage through stack-up simulation and DOE evaluation.
2. Underfill Dispensing Process Risk
Risk Description
- Available dispensing space between package edge and controller die edge is only 610 μm.
- Limited dispensing window may affect underfill flow and process stability.
Potential Impact
- Underfill voids.
- Incomplete filling.
- Yield loss.
Recommended Action
- Conduct underfill dispensing DOE.
- Optimize dispense pattern and process parameters.
3. Strip Warpage Risk
Risk Description
- Thick substrate construction (370 μm) may generate substrate-side bending after underfill curing.
- Excessive strip warpage may affect die bond alignment accuracy.
Potential Impact
- CCD focusing difficulty.
- Die recognition failure.
- Die placement error and X-out.
Recommended Action
- Evaluate strip warpage after underfill curing.
- Perform assembly DOE to verify die bond process window.
4. Substrate Material CTE Mismatch Risk
Risk Description
- High CTE substrate materials may increase thermal stress between substrate and silicon die.
Potential Impact
- Underfill non-wetting.
- Delamination.
- Reliability degradation.
Recommended Action
- Select low-CTE core and prepreg materials.
- Target substrate CTE as close as possible to silicon die CTE (3–5 ppm/°C).
5. Wire Bond Clearance Risk
Risk Description
- Bond pad locations for Dies 2, 3, 6, 7, 31, and 32 are located too close to adjacent die edges.
Potential Impact
- Wire sweep.
- Wire-to-die interference.
- Bonding instability.
Recommended Action
- Recommend customer relocate bond pads further away from die edges.
- Verify wire loop profile through bonding simulation.
6. Thin DRAM Cascade Bonding Risk
Risk Description
- Existing production experience is limited to 45 μm DRAM forward bonding with approximately 630 μm die overhang.
- No prior cascade bonding experience for 45 μm DRAM with 400 μm die overhang configuration.
Potential Impact
- Die crack.
- Die shift.
- Assembly yield risk.
Recommended Action
- Execute DOE evaluation to verify cascade bonding feasibility and process margin.
7. Die Crack Risk Due to Limited Die Spacing
Risk Description
- Die-to-die spacing is limited, increasing mechanical stress during bonding.
Potential Impact
- Die edge crack.
- Silicon damage.
Recommended Action
- Implement cascade bumpless bonding for D3–D4.
- Reduce bonding tool impact frequency on lower dies.
- Verify die integrity through DOE validation.
Overall Assessment
The package structure is technically feasible; however, the design presents elevated risks in the following areas:
- Mold coverage margin.
- Underfill processability.
- Strip warpage after underfill curing.
- Substrate CTE mismatch.
- Wire bond clearance.
- Thin die cascade bonding capability.
- Die crack susceptibility due to limited die spacing.
Process DOE and material optimization are strongly recommended prior to production qualification.
沒有留言:
張貼留言