Reflow soldering process

 Solder paste is used to temporary attach to the anywhere to all the contact pads, after which the assembly is subjected to the controlled heat. Solder paste reflows in a molten state, creating permanent solder joints. Heating can be accomplished by passing the assembly, through a reflow oven.

Usually four stages: preheat,thermal soak, reflow, heating

Preheat zone: climb towards to a target soak, dwell temperature.

Why lead free?

1. Health care

2. Environment: To align with RoHS with the European Union

Tin frequently serves as a principle solder due to its low melting point and excellent wetting properties. Cu & Ag are sometimes added to enhance mechanical strength, and electrical properties of the solder. 

-->Lead based solder: Tin-60%, Pb-40%, melting point:188oC

 -->Lead free Solder: Sn-Ag-Cu, >95% Tin, melting point: 227oC, but less ductile than lead based solder, rendering it has susceptible to mechanical stress, tends to be oxidize more rapidly which can adversely affect its wetting properties and solder joint quality.

What is soldering

A process involves solder, to join together metal surfaces. The solder is heated until it melts and flows into the joint between the two surfaces. Upon cooling, it hardens and forms a reliable electrical and mechanical connection.

Before soldering, the surface of metal should be cleaned thoroughly to remove any oxidations or contaminations that could interfere the formation of a good solder joint.

Vaccum effectively reduce solder void in soldering process

Siemens-EDA Summary

A.Calibre 3D thermal

1.placement & stacking analysis

2.thermal verification :power map 

Simcenter Flotherm : golden tool for 3D thermal simulation & exporting 3D thermal results

Ease of use, designer friendly use, speed, high accuracy providing color maps in 1 day. From simplified power map to final design with detailed power & GDS inputs.

Accuracy: the worst-case difference between simulation and the measured data :3.75%

Customer experince: UMC, TSMC, Intel

B. 3Dblox

Unified format and standardized language

from introduce chiplet detail information, top down to confirm connectivity

C. DFT

scalable from 2D to 3D

die integration & dies at package level

test between dies after AP & diagnosis(in

Complaint with IEEE1149.1, IEEE1500, IEEE1838

Tessant: serial access port composed PTAP/STAP

die wrapper register (DWR) for dies isolation

HBM usually come with IEEE1500 interface, helps to validate the speed of SOC, HBM

bump map, probe map, spacing, die to die , bump analysis, repair method

D: Innovator XPD

macro complex data 

physical reuse- HBM net, auto-replacement, function: rotate, mirror,

original separately process, 500,000 pin can be processed in short time period

tuning in real time, 75% cycle time reduction

 新光電気工業の登録です。    本製品に関する特許も取得しております

チップや能動。受動部品を内蔵した

独自の半導体パックージグ技術を駆使し、優れ電気特性と高い

信頼性を備えた小型　低背パックージとして、小型

iTHOP preshrinkage issue

 The actual shrinkage rate of iTHOP is higher than anticipated, influenced by the smile warpage behavior. The inspection of iTHOP from mark to mark distance was validated that its value is smaller than actual design value. 

Based on our observation, the larger warpage , longer distance between mark to mark, which exhibits more expansion which was validated by the stage DOE experiment from Shinko & PTI. The inner flip chip pad showed that it has higher shrinkage rate, making alignment with the bumping from HBM side challenging.

The thinner organic interposer is more likely to be influenced by the properties of interposer material, it tend to be expand more freely even though vacuumed by the stage, but once bonded, it will be more easily pulled and conformed by ABF substrate.

-->Understanding the interactions can help in optimizing the design to achieve the desired alignment.

3D X ray imaging analysis request

 Since the expansion of substrate during heating with TCB bonding method, different temperature bonding have been studied to reduce the misalignment issue. The effect of temperature is limited, based on 2D X-ray imaging results showed that the farther away from the center, the misalignment value is worsen. We need further analysis with 3D X-ray to analysis if any voids, solder crack after TCB bonding

What is Q3D simulation

Ansys Q3D Extractor is a 3D quasi-static electromagnetic simulation software tool and lumped RLC parameter extractor.  It calculates fields, inductances, resistances, and capacitances. This tools that specializes in low-frequency power applications. It can quickly determine parasitic values of inductance, capacitance, resistance from 3D structures.Q3D can generate frequency dependent equivalent circuit netlists in many formats.

It provides automatic, accurate, and efficietn solution after refining the mesh throughout structure.

HBM offset iTHOP alignment issue

 The offset between HBM and iTHOP is causing the alignment challenges.

Given the differences in expansion between silicon chip and organic interposer substrate, there is potential for cracks or delamination by the high stress generated by the newly formed interconnections. The solder integrity was verified with X-ray and peeling test. The optical observation of the samples after chip pulls on the iTHOP showed that flip chip pad were pulled out with the chip, implying the good adhesion, and hence good joints. Samples were then subjected to reliability stressing to downselect the optimal process for subsequent study.

In the case of TCB process, the substrate is heated and chip joint while it is held to the stage by vacuum.

The large chip size maybe arranged assemmetrically with respect to the center of the substrate. Pads on an organic substrate fluctuate in planar position due to the expansion and contraction of the substrate material as the substrate is heated and cooled. The amount of pad fluctuations varies greatly from place to place.

By applying appropriate compensation in the circuity design of the organic substrate, the micro bumps and pads are designed to align at the temperature at which the solder melts during chip bonding .If the compensation value is not set correctly, it is difficult to ensure good bonding. Even if the center of the chip is perfectly aligned, the further away from the center of the chip, the more serous alignment becomes. If the chip size is small, the degree of misalignment at the edge of the chip will be relatively small. 

The direction of distortion depended on the position of pads.

HBM introduction

The special memory which powering deep learning revolution & AI

MI300: AI acceralator which use HBM

HBM does not refer to a special type of dynamic RAM memory cell or special chip.Rather it is a standard administered by the Joint Electron Device Engineering Council or JEDEC - for interfacing the DRAM and the compute. HBM introduces the concept of stacking the DRAM dies and running many independent memory channels through the stack. The goal is to provide very high data rate transfers for more advanced computing applications like those for AI which are more amenable to parallelism. The vendor can also choose to add a logic base die - as is  shown in the JEDEC spec diagram. This additional logic is for redistributing signals, test logic, and other external commnuncations. JEDEC's standard defines for the manufacturer how the HBM system has to work and what features they need to support. It helps with the commands and signals sent through the memory channel in the DRAM stack, for instance. But it does not specify how the vendor might structure the stack nor does it specify things outside the stack. This allows various HBM vendors in the memory industry to offer a differentiated products. HBM buyers can put your HBM stack right on the top of your CPU or GPU die. Or do what AMD/NVDIA which is to add a silicon interposer to connect multiple HBM die stacks to your GPU-like a PCB. JEDEC also administers other standards like DDR, LPDDR. 

    DDR is the standard you might be most familiar with- used for general purpose memory modules like those you put into your PC. The traditional memory interface standard for graphics cards is GDDR or Graphics Double Data Rate. Right now they are on their sixth generation-GDDR6. There are few gaming cards using it. Why do we need another standard? There are a few things that make it less suitable for heavy AI processing. First, while each new GDDR standard does feature higher data rates, they also employ a point-to-point connection. This means that each memory channel connects to just one module of memory. This is in contrast to HBM, where channels run through all the modules in the stack. GDDR's single channel makes it harder to scale the system's total memory capacity because it means we have to scale that single module's memory capacity which essentially requires us to shrink down DRAM cells even more which is hard, I did a whole video about this while ago discussing the 3D DRAM cell. 

    Future shrinks seem to require new capacitor structures like the pillar which may or may not be actually manufacturable. By vertically stacking the modules, HBM makes it conceptually easy to raise the memory capacity. There are also some physical size gains as well when it 

Reply the concerning about the failure analysis method

    As we know that the samples from substrate side has been grounded down to be thinner, it has resulted in an uneven surface. Due to this uneveneess, when you removed the chip from the top side, the microbump pad may not all to be exposed at the same surface level. This non-uniformity could potentially affect the open short test results as they probably not to make the consistent contact with their corresponding counterparts.

    The thickness of the samples after removing chip also is very concerning. Cold mounting may not be suitable for extremely thin samples. This method cannot precisely targeted to the desired positions or it does not compromise the sample's structural integrital. The air bubbles or voids may form during embedding process, affecting subsequent analysis. It should be more risky than previous PFA proposed by PTI.

    I confirmed with PTI related person, PTI did not have available test kits with fine probe. Anyway,  I still asked these questions to Shinko Japan, we are still waiting their answers. I can predict the answer is not promising.

How to reply customer about the failure analysis time

     At this stage, we are awaiting for internal approvals, which may take some time.

    Once approved are secured, we will expedite the failure analysis procedure and provide you with an estimated completion time for the failure analysis.

UMI HBM P1 PJ preliminary design review

    Today I would like to present a preliminary design phase of the UMI P0 project. The body of the HBM package measures 65x55x4.5mm, the package type is HSFCBGA, it contains 1930 balls. The HBM cube is made of PTI P8 site and the flip chip assembly site is in P11B site. Here is the list of roles related to this project, product engineer is Chris and Sales is Ted.

The purpose of design review is to provide sufficient information, evaluate progress, technical adequacy, and risk resolution of the selected design approach, to determine the each design's compatibility with the requirements for the configuration items, to access the technical risk associated with the selected manufacturing methods and processes, to establish the existence and compatibility of the physical and functional interfaces among the configuration items and other items of equipments, facilities, software, and personnel.

    This is the milestone of UMI P1 project was kicked of by Nov of last year. All drawings have been approved by next month December, and the preliminary design review has been finished on January of this year. We estimate will start the setup & ES from end of May. The HBM cube is made of PTI P8 site and sent to customer for finat testing and return the know good dies to PTI for proceeding the corresponding flow. The cube is diced and secured in metal ring frames, and then transport to another site. And now all the related tooling kits has been arrived at PTI and ready for setup.

    This page demonstrates that the overall P0,P1,P2 project structure, application and status. All of them will be applied for AI or High performance computer. This three project has no big differences but only package size and different wafer node. PTI will start to build HBM cube since from P1 project. UMI managed all the consigned direct material in assembly for the P0 project and has shipped out the package to UMI by end of last year. Estimate to build QT samples from this end of year and HVM will be next year. UMI & PTI are cooperating design drawings rcently.

    The overall project information was published by UMI, which included the HBM, SOC, organic interposer and package substrate. HBM cube of P0 was provided by UMI but customized by UMI in P1 &P2 . All these projects shared the same TSMC SOC wafer with 1pcs wafer. They also shared the same organic interposer with the same 2um/2um line space, 6L and 40/40um line space with 10 layers build up substrate.

    The ES samples of P0 project has been shipped out to UMI before the end of last year. Here is the overall related flow, direct, indirect material & Tooling kits preparation schedule for your reference.

    As we knew that all the material consigned by customer for P0 project, when PTI received the HBM/SOC/ iTHOP, PTI utilized thermocompression bond on iTHOP, and filled the gap between chip and substrate with capillary underfill. The stiffiner ring are bonded on the substrate, and then flipped the package for SMT & ball mounting.

To stack and connect bumped dies in package, PTI uses thermal compression bonding. After peeling the HBM/SOC chip side & iTHOP side, the remained solder amount appeared that the solder joint strength is robust enough. The samples has been executed the cross sectional examination with SEM, the bump gap between chip & iTHOP is close to the design value. The X-ray test results analyzed the placement accuracy of TCB meet the specifications.

     The top director has announced that the 1st HBM cube could be finished by the end of May, the flip chip AP must be ready for setup & ES to meet the development schedule. The lower diagram showed that the basic flow of P1 project, the incoming wafer B will do the microbumps , Backside grinding, wafer mount and dicing, for the incoming A will the PI firstly and then do the microbumps and copper pillar bumps correspondingly. At the BEOL site, PTI mount the die B on the die A with CoW process, and then molding. For the mold grinding, the rough grinding Z1 will be processed in P8 but the fine grinding processed in P11. After grinding, copper pillar bump will be done on the Cu post.

To make a copper bumps, a surface is depostied with an under-bump-metallurgy, then, a photoresist is applied on the UBM, the desired bump size is patterned and etched, forming a small gap in the resist. A copper layer is plated on a surface, forming a pillar in the gap. The material is reflowed or heated, froming the bump.