Why need TSV?

 

    In the package semiconductor sector, through silicon via knowledge and its importance is essential. So today, I would like to talk about TSV technology. It also can called it as 3D package. It is a vertical electrical connection that passes through many types of chipset, from DRAM, NAND, uC, and logic chipsets which contains more than 2 or more chips stacked vertically. It is an alternative to wire bonding and a 2.5D package.

    Compare to 2.5D technology, 3D stacking has more advantages of power consumption, longer bandwidth, higher interconnection density, and the length of connections become shorter.

    Regarding to the manufacturing process, there exist three different types of TSV: via first, via middle and via last. The major process including etching, oxide barrier, barrier seed, plating and CMP. The process of etching is to tench into the silicon, which would act as TSV to fill up TSV material. The critical feature so it is the high aspect ratio, the depth around 100um, and its width is only about 5um. in order to fit in more transistor for more layout efficiency.

    However, there is some responsibilities issue after testing among different chipset process flow and yield rate. If the lower yield rate cannot meet the target, who is to be blamed for it? Therefore it is a very tricky problem for TSV mass production volume.