HBM offset iTHOP alignment issue

 The offset between HBM and iTHOP is causing the alignment challenges.

Given the differences in expansion between silicon chip and organic interposer substrate, there is potential for cracks or delamination by the high stress generated by the newly formed interconnections. The solder integrity was verified with X-ray and peeling test. The optical observation of the samples after chip pulls on the iTHOP showed that flip chip pad were pulled out with the chip, implying the good adhesion, and hence good joints. Samples were then subjected to reliability stressing to downselect the optimal process for subsequent study.

In the case of TCB process, the substrate is heated and chip joint while it is held to the stage by vacuum.

The large chip size maybe arranged assemmetrically with respect to the center of the substrate. Pads on an organic substrate fluctuate in planar position due to the expansion and contraction of the substrate material as the substrate is heated and cooled. The amount of pad fluctuations varies greatly from place to place.

By applying appropriate compensation in the circuity design of the organic substrate, the micro bumps and pads are designed to align at the temperature at which the solder melts during chip bonding .If the compensation value is not set correctly, it is difficult to ensure good bonding. Even if the center of the chip is perfectly aligned, the further away from the center of the chip, the more serous alignment becomes. If the chip size is small, the degree of misalignment at the edge of the chip will be relatively small. 

The direction of distortion depended on the position of pads.

HBM introduction

The special memory which powering deep learning revolution & AI

MI300: AI acceralator which use HBM

HBM does not refer to a special type of dynamic RAM memory cell or special chip.Rather it is a standard administered by the Joint Electron Device Engineering Council or JEDEC - for interfacing the DRAM and the compute. HBM introduces the concept of stacking the DRAM dies and running many independent memory channels through the stack. The goal is to provide very high data rate transfers for more advanced computing applications like those for AI which are more amenable to parallelism. The vendor can also choose to add a logic base die - as is  shown in the JEDEC spec diagram. This additional logic is for redistributing signals, test logic, and other external commnuncations. JEDEC's standard defines for the manufacturer how the HBM system has to work and what features they need to support. It helps with the commands and signals sent through the memory channel in the DRAM stack, for instance. But it does not specify how the vendor might structure the stack nor does it specify things outside the stack. This allows various HBM vendors in the memory industry to offer a differentiated products. HBM buyers can put your HBM stack right on the top of your CPU or GPU die. Or do what AMD/NVDIA which is to add a silicon interposer to connect multiple HBM die stacks to your GPU-like a PCB. JEDEC also administers other standards like DDR, LPDDR. 

    DDR is the standard you might be most familiar with- used for general purpose memory modules like those you put into your PC. The traditional memory interface standard for graphics cards is GDDR or Graphics Double Data Rate. Right now they are on their sixth generation-GDDR6. There are few gaming cards using it. Why do we need another standard? There are a few things that make it less suitable for heavy AI processing. First, while each new GDDR standard does feature higher data rates, they also employ a point-to-point connection. This means that each memory channel connects to just one module of memory. This is in contrast to HBM, where channels run through all the modules in the stack. GDDR's single channel makes it harder to scale the system's total memory capacity because it means we have to scale that single module's memory capacity which essentially requires us to shrink down DRAM cells even more which is hard, I did a whole video about this while ago discussing the 3D DRAM cell. 

    Future shrinks seem to require new capacitor structures like the pillar which may or may not be actually manufacturable. By vertically stacking the modules, HBM makes it conceptually easy to raise the memory capacity. There are also some physical size gains as well when it 

Reply the concerning about the failure analysis method

    As we know that the samples from substrate side has been grounded down to be thinner, it has resulted in an uneven surface. Due to this uneveneess, when you removed the chip from the top side, the microbump pad may not all to be exposed at the same surface level. This non-uniformity could potentially affect the open short test results as they probably not to make the consistent contact with their corresponding counterparts.

    The thickness of the samples after removing chip also is very concerning. Cold mounting may not be suitable for extremely thin samples. This method cannot precisely targeted to the desired positions or it does not compromise the sample's structural integrital. The air bubbles or voids may form during embedding process, affecting subsequent analysis. It should be more risky than previous PFA proposed by PTI.

    I confirmed with PTI related person, PTI did not have available test kits with fine probe. Anyway,  I still asked these questions to Shinko Japan, we are still waiting their answers. I can predict the answer is not promising.

How to reply customer about the failure analysis time

     At this stage, we are awaiting for internal approvals, which may take some time.

    Once approved are secured, we will expedite the failure analysis procedure and provide you with an estimated completion time for the failure analysis.